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The external device then processes the available data and pulses the STRA line to indicate that new data may be placed on the port C output lines. The active edge on the STRA line causes the STRB line to be deasserted and the STAF status flag to be set. In response to the STAF bit being set, the program transfers new data out of port C as required. Writing data to the PORTCL register causes the data to appear on port C lines and asserts the STRB line. There is a variation to the output handshake protocol that allows three-state operation on port C.
At the completion of transmitting a byte of data, the SPIF status bit is set in both the master and slave devices. When the user reads the serial peripheral data l/O register, a buffer is actually being read. The first SPIF must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated or an overrun condition will exist. In cases of overrun the byte which causes the overrun is lost. A write to the serial peripheral data l/O register is not buffered and places data directly into the shift register for transmission.
SCK CYCLE # (FOR REFERENCE) 1 2 3 4 5 6 7 8 SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE INPUT (CPHA = 0) DATA OUT MSB 6 5 4 3 2 1 LSB SAMPLE INPUT (CPHA = 1) DATA OUT MSB 6 5 4 3 2 1 LSB SS (TO SLAVE) SPI TRANSFER FORMAT Figure 6-1 Data Clock Timing Diagram When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock phase mode, SS must go high between successive characters in an SPI message. When CPHA = 1, SS may be left low for several SPI characters. In cases where there is only one SPI slave MCU, its SS line could be tied to VSS as long as CPHA = 1 clock modes are used.
68HC11 Technical Docs